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Simulación digital para verificación de diseño y sus aplicaciones en el desarrollo de pruebas automatizadas

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PUPR_SJU_CEAH_Publicaciones_Revista UPPR_Vol02_Num01_Junio 1992_P01_Rafael A. Figueroa_Rodolfo E. Jordán_Article (898.4Kb)
Date
1992-06
Author
Figueroa, Rafael A.
Jordán, Rodolfo E.
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Abstract
This paper presents the digital simulator as the tool for the computerized analysis of digital logic circuits. Among the topics discussed in the study are the behaviour of digital circuits, the development of vectors to test automated equipment, the fault principle to test digital circuits and the use of models to simulate the digital logic. The logic simulator driven by events is studied in detail and some advices on how to implant a logical simulator are given.
URI
http://hdl.handle.net/20.500.12475/1439
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